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<title>MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value </title></head>
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<h1>MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F2 0F 10 /r</p>
<p>MOVSD xmm1, xmm2</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double-precision floating-point value from xmm2 to xmm1 register.</td></tr>
<tr>
<td>
<p>F2 0F 10 /r</p>
<p>MOVSD xmm1, m64</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Load scalar double-precision floating-point value from m64 to xmm1 register.</td></tr>
<tr>
<td>
<p>F2 0F 11 /r</p>
<p>MOVSD xmm1/m64, xmm2</p></td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move scalar double-precision floating-point value from xmm2 register to xmm1/m64.</td></tr>
<tr>
<td>
<p>VEX.NDS.LIG.F2.0F.WIG 10 /r</p>
<p>VMOVSD xmm1, xmm2, xmm3</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double-precision floating-point value from xmm2 and xmm3 to xmm1 register.</td></tr>
<tr>
<td>
<p>VEX.LIG.F2.0F.WIG 10 /r</p>
<p>VMOVSD xmm1, m64</p></td>
<td>XM</td>
<td>V/V</td>
<td>AVX</td>
<td>Load scalar double-precision floating-point value from m64 to xmm1 register.</td></tr>
<tr>
<td>
<p>VEX.NDS.LIG.F2.0F.WIG 11 /r</p>
<p>VMOVSD xmm1, xmm2, xmm3</p></td>
<td>MVR</td>
<td>V/V</td>
<td>AVX</td>
<td>Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1.</td></tr>
<tr>
<td>
<p>VEX.LIG.F2.0F.WIG 11 /r</p>
<p>VMOVSD m64, xmm1</p></td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Store scalar double-precision floating-point value from xmm1 register to m64.</td></tr>
<tr>
<td>
<p>EVEX.NDS.LIG.F2.0F.W1 10 /r</p>
<p>VMOVSD xmm1 {k1}{z}, xmm2, xmm3</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.LIG.F2.0F.W1 10 /r</p>
<p>VMOVSD xmm1 {k1}{z}, m64</p></td>
<td>T1S-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Load scalar double-precision floating-point value from m64 to xmm1 register under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.LIG.F2.0F.W1 11 /r</p>
<p>VMOVSD xmm1 {k1}{z}, xmm2, xmm3</p></td>
<td>MVR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.LIG.F2.0F.W1 11 /r</p>
<p>VMOVSD m64 {k1}, xmm1</p></td>
<td>T1S-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Store scalar double-precision floating-point value from xmm1 register to m64 under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>XM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MVR</td>
<td>ModRM:r/m (w)</td>
<td>vvvv (r)</td>
<td>ModRM:reg (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S-RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>T1S-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Moves a scalar double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. This instruction can be used to move a double-precision floating-point value to and from the low quadword of an XMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.</p>
<p>Legacy version: When the source and destination operands are XMM registers, bits MAX_VL:64 of the destination operand remains unchanged. When the source operand is a memory location and destination operand is an XMM registers, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAX_VL:128 of the desti-nation operand remains unchanged.</p>
<p>VEX and EVEX encoded register-register syntax: Moves a scalar double-precision floating-point value from the second source operand (the third operand) to the low quadword element of the destination operand (the first operand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand). Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.</p>
<p>VEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination operand is an XMM registers, bits MAX_VL:64 of the destination operand is cleared to all 0s.</p>
<p>EVEX encoded versions: The low quadword of the destination is updated according to the writemask.</p>
<p>Note: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instruction will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VMOVSD (EVEX.NDS.LIG.F2.0F 10 /r: VMOVSD xmm1, m64 with support for 32 registers)</strong></p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) SRC[63:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[511:64] (cid:197) 0</p>
<p><strong>VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD m64, xmm1 with support for 32 registers)</strong></p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) SRC[63:0]</p>
<p>ELSE</p>
<p>*DEST[63:0] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p><strong>VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)</strong></p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) SRC2[63:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[63:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[63:0] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>DEST[127:64] (cid:197) SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>MOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[MAX_VL-1:64] (Unmodified)</p>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)</strong></p>
<p>DEST[63:0] (cid:197)SRC2[63:0]</p>
<p>DEST[127:64] (cid:197)SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)</strong></p>
<p>DEST[63:0] (cid:197)SRC2[63:0]</p>
<p>DEST[127:64] (cid:197)SRC1[127:64]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[MAX_VL-1:64] (cid:197)0</p>
<p><strong>MOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p><strong>MOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[127:64] (cid:197)0</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);</p>
<p>VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);</p>
<p>VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);</p>
<p>VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);</p>
<p>VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);</p>
<p>MOVSD __m128d _mm_load_sd (double *p)</p>
<p>MOVSD void _mm_store_sd (double *p, __m128d a)</p>
<p>MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5; additionally</p>
<table>
<tr>
<td>#UD</td>
<td>
<p>If VEX.vvvv != 1111B.</p>
<p>EVEX-encoded instruction, see Exceptions Type E10.</p></td></tr></table></body></html>